STMicroelectronics has redefined the bar for ultra-low-power microcontrollers with the STM32U5 series, its most significant advancement in the STM32 ultra-low-power portfolio since the original STM32L1 launched in 2009. Built around the Arm Cortex-M33 core with TrustZone for Armv8-M, the STM32U5 delivers 160 MHz performance while achieving industry-leading power efficiency—down to 19 μA/MHz in run mode and just 110 nA in shutdown. But the real story isn’t just power: it’s security. The STM32U5 is the first general-purpose MCU to achieve both PSA Certified Level 3 and SESIP Level 3 certifications, making it a compelling choice for IoT edge devices, wearables, medical sensors, and payment terminals that demand both battery life and tamper resistance.
The STM32U5 Family: A Product Matrix for Every Need
The STM32U5 series spans multiple sub-families, each targeting different application requirements:
| Series | Flash / SRAM | Key Differentiator | Security Features |
|---|---|---|---|
| STM32U535 | 128-512 KB / up to 256 KB | Entry-level, cost-optimized | TrustZone only |
| STM32U545 | 512 KB / up to 256 KB | Mid-range with crypto | TrustZone + AES + PKA |
| STM32U575 | 1-2 MB / 786 KB | High integration | TrustZone + AES + PKA |
| STM32U585 | 2 MB / 786 KB | Full security suite | TrustZone + AES + PKA + OTFDEC |
| STM32U595 | 2-4 MB / 2.5 MB | Large memory, graphics | TrustZone + NeoChrom GPU |
| STM32U5A5 | 4 MB / 2.5 MB | Max memory + security | Full suite + NeoChrom GPU |
The STM32U595/U5A5 variants represent the largest on-chip memory ever offered in an STM32 MCU: 4 MB Flash and 2.5 MB SRAM, sufficient to run sophisticated GUIs and data-intensive applications without external memory.
Core Architecture: Cortex-M33 with TrustZone
The STM32U5 is built on the Arm Cortex-M33 processor, the first Cortex-M core to implement the Armv8-M architecture with TrustZone-M security extensions. Key features include:
- 160 MHz maximum frequency with single-cycle multiply and hardware divide
- TrustZone for Armv8-M — hardware-enforced isolation between Secure and Non-secure code, without the performance overhead of software-based separation
- Single-precision FPU (IEEE 754 compliant)
- DSP instructions — saturating arithmetic, SIMD operations
- ART Accelerator — ST’s proprietary instruction cache technology for near-zero wait-state Flash access
TrustZone-M differs significantly from the TrustZone-A implementation in Cortex-A processors. It’s designed specifically for deeply embedded real-time systems, with deterministic behavior and minimal latency overhead. The hardware enforces memory access permissions at the bus level—Secure code can access all memory, while Non-secure code is restricted to Non-secure regions. This creates a hardware root of trust for secure boot, cryptographic key storage, and firmware update mechanisms.
Security: PSA Level 3 and SESIP Level 3 Certified
The STM32U585 achieved a milestone: PSA Certified Level 3 and SESIP Level 3 certifications. These are not marketing claims—they represent independent, laboratory-verified security assurance:
- PSA Certified Level 3 — Arm’s Platform Security Architecture certification, requiring hardware root of trust, secure boot, secure firmware update, and attestation capabilities. Level 3 adds software isolation testing.
- SESIP Level 3 — Security Evaluation Standard for IoT Platforms, an independent lab assessment covering logical, board-level, and basic physical attack resistance.
The security subsystem includes:
Cryptographic Accelerators
- AES-128/256 engine with side-channel attack (DPA) resistance
- Public Key Accelerator (PKA) — RSA, ECC, Diffie-Hellman operations with DPA hardening
- HASH hardware — SHA-1, SHA-224, SHA-256
- True Random Number Generator (TRNG) — NIST SP 800-90B compliant entropy source
On-The-Fly Decryption (OTFDEC)
A unique feature in STM32U585/U5A5: OTFDEC allows encrypted code and data to be stored in external Octo-SPI Flash, decrypted in real-time as the CPU fetches it. This enables:
- Secure firmware distribution — IP protection for third-party code
- Secure asset storage — encrypted graphics assets, ML models, calibration data
- Four independent decryption regions with separate keys
Tamper Detection and Active Zeroization
- Active tamper detection — internal monitoring for voltage glitching, clock manipulation, and temperature attacks
- Automatic key erasure — on tamper event detection, cryptographic keys are zeroized before an attacker can extract them
- Hardware Unique Key (HUK) — device-specific key for secure data storage, never exposed to software
This tamper resistance makes STM32U585 suitable for PCI PTS-compliant payment terminals—a domain traditionally requiring separate secure element chips.
Ultra-Low-Power: The LPBAM Innovation
The STM32U5 introduces Low Power Background Autonomous Mode (LPBAM), a paradigm shift in how peripherals interact with the CPU:
In traditional low-power MCUs, when the CPU enters Stop or Standby mode, most peripherals stop functioning. If a sensor needs to be sampled or data received over UART, the CPU must wake up—burning precious energy.
LPBAM changes this: peripherals can continue operating autonomously while the CPU remains in Stop mode. The dedicated LPDMA (Low-Power DMA) can transfer data between peripherals and SRAM without CPU intervention. Supported peripherals include:
- LPUART, LPI2C, LPSPI — low-power serial interfaces
- LPTIM — low-power timers
- ADC — analog-to-digital conversion
- SPI/I2S — for audio data streaming
Real-world impact: a wearable device can continuously sample an accelerometer at 100 Hz and store data to SRAM, while the CPU stays in Stop 2 mode consuming just 6.6 μA. The CPU only wakes when a threshold is crossed or a buffer is full.
Power Consumption Benchmarks
| Mode | Current | Notes |
|---|---|---|
| Shutdown | 110 nA | Minimal retention |
| Standby | 300 nA | RTC + backup registers |
| Stop 3 | 1.7 μA | 16 KB SRAM retention |
| Stop 2 | 6.6 μA | 786 KB SRAM retention |
| Run (LDO) | 19 μA/MHz | Dynamic consumption |
| Run (SMPS) | ~13 μA/MHz | With internal DC/DC |
Optional Internal SMPS
Variants with a “Q” suffix (e.g., STM32U585AIQ) include an integrated switch-mode power supply (SMPS) buck converter. The SMPS improves efficiency by ~30% compared to the internal LDO, especially at higher clock frequencies. The SMPS and LDO can be dynamically switched at runtime—use SMPS for compute-intensive tasks, switch to LDO for noise-sensitive ADC sampling.
Peripherals and Integration
Analog
- 14-bit ADC — up to 2.5 MSPS, a first for STM32 (previous max was 12-bit)
- 12-bit ADC — multiple instances
- 12-bit DAC — dual channel
- Op-amps and comparators — internal, for signal conditioning without external components
Digital Filters
- MDF (Multi-function Digital Filter) — configurable decimation, CIC filters for sigma-delta modulators
- ADF (Audio Digital Filter) — PDM microphone interface with hardware decimation
Graphics (U595/U5A5/U5F9/U5G9)
- NeoChrom VG GPU — ST’s second-generation 2.5D vector graphics accelerator
- ChromART Accelerator — DMA2D for pixel manipulation
- JPEG codec — hardware encode/decode
The NeoChrom GPU enables smartphone-style UIs on a microcontroller—vector graphics, SVG rendering, smooth animations—without an external GPU or display controller.
Connectivity
- USB OTG Full-Speed with integrated PHY
- USB High-Speed with integrated PHY (U595/U5A5)
- Octo-SPI and Hexadeca-SPI for external memory
- FSMC for parallel NOR/SRAM/NAND
- I2C, SPI, USART, LPUART in abundance
Manufacturing Technology: 40 nm Process
The STM32U5 is manufactured on ST’s 40 nm embedded Flash process. This is a significant advance from the 90 nm and 65 nm processes used for earlier STM32L generations. The smaller geometry enables:
- Higher density — 4 MB Flash in a single chip
- Lower dynamic power — reduced capacitance at smaller nodes
- Cost efficiency — more die per wafer
The 40 nm node is mature and stable for embedded Flash, with proven reliability for automotive and industrial applications.
Development Ecosystem
STM32U5 is fully supported by ST’s mature toolchain:
- STM32CubeIDE — free Eclipse-based IDE with GCC toolchain
- STM32CubeMX — graphical configuration and code generation
- STM32CubeProgrammer — Flash programming and debug
- STM32CubeU5 — HAL, LL drivers, middleware, and examples
- Trusted Firmware-M (TF-M) — PSA-compliant secure firmware reference implementation
- Azure RTOS — pre-integrated and certified
- FreeRTOS — pre-integrated with AWS IoT connectivity
Development Boards
- B-U585I-IOT02A — Discovery kit for IoT nodes, with sensors, Wi-Fi, and cloud connectivity
- NUCLEO-U575ZI-Q — Nucleo-144 board for general development
- STM32U5G9J-DK — Discovery kit with NeoChrom GPU and TouchGFX for GUI development
Target Applications
- Wearables — smart watches, fitness trackers, health monitors (LPBAM enables always-on sensing)
- Medical devices — glucose monitors, pulse oximeters, drug delivery (PSA Level 3 for data protection)
- Payment terminals — POS, card readers (PCI PTS compliance support)
- Industrial sensors — condition monitoring, predictive maintenance
- Smart home — thermostats, door locks, appliances
- Consumer electronics — smart speakers, e-bikes, toys with GUIs
Pricing and Availability
The STM32U5 series is in volume production. Pricing starts at approximately $3-5 for entry-level U535 variants in 10K quantities, scaling to $15-25 for U5A5 with full memory and graphics. All variants are offered with ST’s 10-year longevity guarantee for industrial and automotive applications.
Resources
- Product Page: st.com/en/microcontrollers-microprocessors/stm32u5-series
- STM32CubeU5: github.com/STMicroelectronics/STM32CubeU5
- Trusted Firmware-M: trustedfirmware.org/projects/tf-m
- TouchGFX: touchgfx.com